发明名称 |
Method and system for reducing hysteresis effect in SOI CMOS circuits |
摘要 |
A method for reducing a hysteresis effect in silicon-on-insulator CMOS circuits includes the steps of providing a circuit having CMOS objects, defining a beta ratio; resizing the CMOS objects based on the beta ratio, determining if the objects are a minimum size based on predetermined size criteria, if the objects are larger than the minimum size, defining a scaling factor based on a performance level of the object and resizing the object based on the scaling factor such that delay variations of the resized circuit are substantially constant. Also, a computer program product is provided for reducing the hysteresis effect.
|
申请公布号 |
US6298467(B1) |
申请公布日期 |
2001.10.02 |
申请号 |
US19980189423 |
申请日期 |
1998.11.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHUANG CHING-TE K.;PELELLA MARIO M.;TRETZ CHRISTOPHE R. |
分类号 |
G06F17/50;H01L27/12;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|