| 摘要 |
A method for fabricating source/drain and gate of a TFT (thin film transistor) array is disclosed herein. After depositing multi-layer structures according to the present invention, an etching process is performed to define source/drain or gate of a TFT array and an excellent taper profile is easily obtained even though only the prior art etchant is used. The method for depositing multi-layer structures includes the following steps. Firstly, form a major conductive metallic layer on the substrate or on the previous layers depending on whether gate or source/drain bus is to be formed, then form a barrier layer on the metallic layer with dopant doped into the barrier layer. It is noted that the concentration of the dopant has a gradient distribution, and has a maximum value at the edge of the barrier layer adjacent to the metallic layer. The first edge of the barrier layer adjacent to the metallic layer has a first dopant concentration, and the second edge of the barrier layer farther from the metallic layer has a second dopant concentration. The first dopant concentration is greater than the second dopant concentration. A special feature of this structure is that the wet etching rate of the doped barrier layer can be modulated by the doping concentration. Specifically, the higher the doping concentration, the lower the etching rate is preferred. Because the etching rate of the barrier layer is gradient changed by modulating the doping concentration during film deposition, the taper profile of the barrier layer will be automatically formed without the adjustment of the adhesion to the resist mask. It makes the etching chemistry less complicated and the profile is not sensitive to the bath life. Another feature of this method is that the etching rate of the barrier layer should be higher than the major metallic conductive layer to avoid the negative slope of the profile.
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