发明名称 INTERLEAVE ADDRESS GENERATOR
摘要 PROBLEM TO BE SOLVED: To provide an interleave address generator that can relieve a processing load for generating an interleave pattern in the case of generating a Prime interleave address. SOLUTION: A memory address generator 12 generates a memory address, a multiplier 15 reads a replacement pattern of a row corresponding to a row number, outputted from a row counter 11, from a memory 14 storing the replacement pattern to rows of a matrix, multiplies the replacement pattern of the read row with the column number of the matrix to calculate an address offset. An adder 16 reads the replacement pattern of a column corresponding to a memory address generated by the memory address generator from a memory 13 storing the replacement pattern of the column of the matrix, and sums the replacement pattern of the read column to the address offset to generate an interleave address.
申请公布号 JP2001267934(A) 申请公布日期 2001.09.28
申请号 JP20000076879 申请日期 2000.03.17
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IKEDA TETSUYA;SUZUKI HIDETOSHI;YAMANAKA RIYUUTAROU;KURIYAMA HAJIME
分类号 G06F11/10;G11C8/00;G11C29/00;H03M13/27;H04B14/04;H04L1/00;(IPC1-7):H03M13/27 主分类号 G06F11/10
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