发明名称 CHIP-TYPE LAMINATED VARISTOR
摘要 PROBLEM TO BE SOLVED: To provide a chip-type laminated varistor which is mainly composed of SrTiO3 and protected against cracking at soldering. SOLUTION: A ceramic layer 3 mainly composed of calcined SrTiO3 of grain diameter 0.6 to 0.7 μm and inner electrodes layers 4 and 5 whose main components are NiO are alternately laminated into a laminate, and the laminate is baked into a sintered body 2, and outer electrodes are provided to the sintered body 2 for the formation of a chip-type laminated varistor 1, where the above NiO particles have such a grain diameter distribution that 10% average grain diameter (D10) is 0.40 to 0.45 μm, 50% average grain diameter (D50) is 0.70 to 0.80 μm, and 90% average grain diameter (D90) is 1.50 to 1.65 μm.
申请公布号 JP2001267107(A) 申请公布日期 2001.09.28
申请号 JP20000076205 申请日期 2000.03.17
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 AMISAWA MIKINORI
分类号 C04B35/46;H01C7/10 主分类号 C04B35/46
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