| 摘要 |
PROBLEM TO BE SOLVED: To minimize delay variance due to parallel wiring which is generated in automatic wiring even on a chip whose needs to be wired is high to some extent as to the mounting design of a semiconductor integrated circuit. SOLUTION: The ratio of wires allocated by rough wiring in each horizontal divided area to the number of channels prepared in the divided area is computed and when the ratio is less than a certain ratio (e.g. <=50%), detailed wiring is carried out using wiring tracks alternately. When the ratio is larger than the certain value (e.g. >50%), detailed wiring is carried out by excluding one wire from objects of wiring allocation for every 3rd wiring track, namely, arranging two wiring tracks as objects of wiring allocation between one wiring track excluded from the objects of wiring allocation and the next wiring track excluded from the objects of wiring allocation.
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