| 摘要 |
PROBLEM TO BE SOLVED: To provide a synchronization detector that can detect a frame synchronization pattern with high accuracy and reduce the scale of the hardware by relaxing an arithmetic speed being a requirement in complex correlation processing. SOLUTION: Analog/digital converters 107a, 107b apply analog/digital conversion to a signal for a complex base band including frame synchronization data, a correlation filter 121 output a complex correlation between the signal sequence after the conversion and the frame synchronization pattern stored in a storage section 111, over-sampling means 122a, 122b divides the complex correlation, square means 123a, 123b obtain a square of its in-phase component signal sequence and its quadrature component signal sequence, an adder 124 sums the squares, and a generating means 108 decides the signal sequence to be the frame synchronization data when a threshold decision means 125 decides that the complex correlation of the square sum is a specified value or over so as to synchronize reception timing and a reception clock with the received frame synchronization pattern. |
