发明名称 BIT SYNCHRONIZATION CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a bit synchronization circuit that can have no dead band phase, instantaneously establish synchronization, and can be in operation even at a high-speed bit rate of 10 Gb/s or over. SOLUTION: The bit synchronization circuit of this invention is characterized in that a phase and an amplitude of a data signal are compared with those of a reference clock signal to instantaneously establish bit synchronization, the circuit is configured with a simple logic, the bit synchronization is instantaneously established because of absence of a feedback loop, the phase of the data signal is analogically compared with the phase of the clock signal, and sampling and holding the result of the phase comparison receives no limitation of a preamble pattern.</p>
申请公布号 JP2001268061(A) 申请公布日期 2001.09.28
申请号 JP20000081167 申请日期 2000.03.23
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 ONODERA KIYOMITSU
分类号 H04L7/027;(IPC1-7):H04L7/027 主分类号 H04L7/027
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