发明名称 MROM CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a MROM circuit in which erroneous read operations based on capacity coupling between bit lines are not caused and which has a large scale and high integration density, and which can be operated by low voltage. SOLUTION: In this MROM circuit, discharge transistors for fixing non- selection bit lines always to '0' are connected to each bit line to prevent the occurrence of erroneous read operations based on capacity coupling between bit lines owing to discharge of adjacent bit lines. Further, by providing a holding circuit holding data '1' read out to a pre-bit line as static data '1' in a time other than a pre-charge period in a read section of ROM data, a large scale MROM circuit, which has high density, large capacity, and which can be operated by low voltage can be provided using a process of making a circuit more minute.</p>
申请公布号 JP2001266585(A) 申请公布日期 2001.09.28
申请号 JP20000082589 申请日期 2000.03.23
申请人 TOSHIBA LSI SYSTEM SUPPORT KK;TOSHIBA CORP 发明人 OIKAWA KIYOHARU
分类号 G11C17/18;(IPC1-7):G11C17/18 主分类号 G11C17/18
代理机构 代理人
主权项
地址