| 摘要 |
PROBLEM TO BE SOLVED: To realize a reduction of layout area guaranteeing the stability of holding data in a static semiconductor memory. SOLUTION: This SRAM cell is constituted of two MOS transistors 10 and 12 and one inversion circuit 14. In the PMOS transistor 10, a source terminal is connected to a bit line BL, a drain terminal is connected to a data storage node Na, and a gate terminal is connected to a word line WL. In the N MOS transistor 12, a source terminal is connected to a power source voltage terminal giving a reference potential Vss (e.g. zero volt) of L level, a drain terminal is connected to a data storage node Na, and a gate terminal is connected to an output terminal of the inversion circuit 14. An input terminal of the inversion circuit 14 is connected to the data storage node Na.
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