发明名称 MANUFACTURING METHOD FOR INSULATED-GATE FIELD-EFFECT TRANSISTOR
摘要 PROBLEM TO BE SOLVED: To solve the problem where a pattern width cannot be made sufficiently small, because a first offset region and a second offset region are formed by a photolithographic process and that there is a limit to reduction in on- resistance. SOLUTION: A semiconductor substrate, which comprises a p-type single- crystal silicon semiconductor substrate 1, a silicon oxide film 2 and a single- crystal silicon semiconductor layer 3 is used. Ions are implanted and diffused, a p-type channel region 4 is formed, and a gate oxide film 5, a polycrystalline silicon film 6 and an oxide film 7 are formed. Ions are implanted, a first n-type offset region 8 and an n-type source region 9 are formed, and a silicon nitride film 10 and a silicon oxide film 11 are deposited. The silicon oxide film 11 is worked by an anisotropic etching operation, and the silicon nitride film 10 is worked by a chemical etching operation. Ions are implanted, and the second offset region 12 is formed. A silicon oxide film 13 is deposited, and it is worked by an anisotropic etching operation. Ions are implanted and diffused, and the n-type source region 9 and an n-type drain region 14 are formed. An interlayer film 15 and electrode 16 to 18 are formed.
申请公布号 JP2001267585(A) 申请公布日期 2001.09.28
申请号 JP20000081628 申请日期 2000.03.23
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 MATSUMOTO SATOSHI;SAKAI TATSURO
分类号 H01L21/28;H01L21/336;H01L29/786;(IPC1-7):H01L29/786 主分类号 H01L21/28
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