LOGIC VERIFICATION SYSTEM

摘要

PROBLEM TO BE SOLVED: To efficiently confirm the operation of a logic circuit when a fault of logical operation is detected by simulation by using a logic simulation result file with small capacity. SOLUTION: A logic simulation execution part 108 performs logic simulation by using logic circuit information 102, simulation execution control information 103, and state data 104 and obtained signal value variation information on an object logic circuit is stored in a simulation result (temporary) file 106; and a simulation result comparison part 101 compares the signal value variation information stored in the file with previously set expected value information. When they do not match each other, the signal value variation information stored in the simulation result (temporary) file 106 from the time which is a previously specified output range time before their discrepancy is generated until the discrepancy is generated is stored in a simulation result and the subsequent logic simulation is stopped.