| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit that is easily integrated as an LSI with a short lockup time, less power consumption, and high C/N. SOLUTION: The PLL circuit is provided with a variable frequency divider PD that divides a frequency of an output signal from a voltage controlled oscillator VCO with a frequency division rate of N+B/C (N, B, C are integers and B<=C) and provides an output of a feedback signal and with phase comparators PC1, PC2 that compare a phase of the reference signal with a phase of the feedback signal. The phase comparators PC1, PC2 conduct normal phase comparison once per C times. |
