发明名称 MEMORY PAUSE TEST CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD
摘要 PROBLEM TO BE SOLVED: To solve such a problem that when memory macro-cells of various kinds incorporated in a semiconductor integrated circuit are tested and a pause test is performed, it takes a long time to perform testing successively. SOLUTION: There is a test method using a BIST circuit in a method for testing a memory macro-cell, but in order to perform efficiently and easily a pause test of many memory macro-cells incorporated in a semiconductor integrated circuit, such a circuit other than the BIST circuit is incorporated in the semiconductor integrated circuit that memory macro-cells of which address directions are the same are made a unit with which control is performed by the BIST, even if a time for writing a checker pattern in the memory macro- cell being timing of pause is different depending on BIST controllers, the circuit that makes the BIST controller wait until a checker patter is written in the BIST controller is mounted on the semiconductor integrated circuit in addition to the BIST controller.
申请公布号 JP2001266594(A) 申请公布日期 2001.09.28
申请号 JP20000084344 申请日期 2000.03.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KINOSHITA TAKASHI
分类号 G01R31/28;G06F11/22;G06F12/16;G11C29/00;G11C29/12;G11C29/34 主分类号 G01R31/28
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