发明名称 Write cache circuit, recording apparatus with write cache circuit, and write cache method
摘要 User data transmitted from the host side is first stored in write cache regions of an SDRAM 12 on the basis of an error correction process. When executing an ECC.EDC encode process of adding redundancy data such as an error correction code to the stored user data on the basis of the error correction processing, an encode region of SDRAM 12 is used. The data subjected to the ECC.EDC encode process is sequentially read out from encode region to be modulated and then written onto a disk.
申请公布号 US2001025334(A1) 申请公布日期 2001.09.27
申请号 US20010805940 申请日期 2001.03.15
申请人 SANYO ELECTRIC CO., LTD. 发明人 FUMA MASATO;OKAMOTO MIYUKI
分类号 G06F12/08;G06F3/06;G06F12/16;G11B20/10;G11B20/18;G11B27/19;G11B27/24;G11B27/30;(IPC1-7):G06F12/00 主分类号 G06F12/08
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