发明名称 Error detection and correction method in a computer system and main memory controller of the same
摘要 According to an error detection and correction method to be implemented in a computer system, when an error is detected in data to be written in a memory, fault information is appended to the data without an increase in the number of bits constituting the data, and the resultant data is stored in the memory. An error control code represented by a SEC-DEC code is adopted for encoding and decoding. Data is encoded into a shortened code. At this time, specific bit positions associated with column vectors deleted from a parity check matrix defined in the error control code are allocated to fault information. Thus, a word to be actually stored in the memory is composed of check bits produced from data to be written and fault information, and information bits constituting the data to be written. Decoding is performed on the assumption that the fault information represents 0s. When data having fault information appended thereto is decoded, the fault information is reproduced through error detection and correction.
申请公布号 US2001025359(A1) 申请公布日期 2001.09.27
申请号 US20010805169 申请日期 2001.03.14
申请人 TANAKA TSUYOSHI 发明人 TANAKA TSUYOSHI
分类号 G06F11/10;G06F3/06;G06F12/16;H03M13/01;H03M13/15;(IPC1-7):H03M13/05 主分类号 G06F11/10
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