摘要 |
For each sync frame, an AND circuit detects whether a pre-pit synchronization signal can be obtained within a window set by a timing generator. Detection result of the AND circuit is held by a shift register, where it is shifted in response to each sync frame. On the basis of a parallel output from the shift register, a decoder determines whether the detection of the pre-pit synchronization signal is accurate or erroneous. Count value of a counter is incremented by one each time the decoder determines that the detection of the pre-pit synchronization signal is accurate, but is decremented by one each time the decoder determines that the detection of the pre-pit synchronization signal is erroneous. Identification section identifies stability/instability of the pre-pit synchronization signal detection.
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