| 摘要 |
<p>A high-performance delta sigma analog-to-digital converter (90). The high-performance delta sigma analog-to-digital converter (90) includes a first mechanism (12, 52, 38, 16, 92) for converting an input analog signal (26) to a digital output signal (44). The first mechanism (12, 52, 38, 16, 92) is characterized by a transfer function that is altered relative to an ideal transfer function. A second mechanism (86, 88, 92) compensates for the alteration in the transfer function via a single additional digital-to-analog converter (88). In a specific embodiment, the alteration includes an additional pole and an additional zero induced by feedback delays in the first mechanism (12, 52, 38, 16, 92). The feedback delays include signal dependent jitter delay and feedback digital-to-analog converter cell switching delays. The second mechanism (86, 88, 92) includes an additional latch (86) that compensates for the signal dependent jitter delay. The first mechanism (12, 52, 38, 16, 92) includes a resonator (12, 52) and a quantizer (16). The second mechanism (86, 88, 92) includes a feedback path (92) from an output of the quantizer (16) to the resonator (52). The feedback path (92) includes a first latch (18) positioned between an output of the quantizer (16) and the additional digital-to-analog converter (88). The additional latch (86) is positioned at an output of the first latch (18) and eliminates signal dependent jitter delay in the analog-to-digital converter (90). The additional feedback digital-to-analog converter (88) is a non-return-to-zero digital-to-analog converter, an output of which is connected to the resonator.</p> |
