发明名称 |
Symbol based algorithm for hardware implementation of cyclic redundancy check |
摘要 |
A method and apparatus for generation of CRC generation/checker circuitry. A symbolic simulation-based algorithm to derive boolean equations for a parameterizable data-width CRC generator/checker is described. The equations generated are used to implement a data-flow representation of the CRC circuit in VHDL. The VHDL description is then synthesized into gates.
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申请公布号 |
US6295626(B1) |
申请公布日期 |
2001.09.25 |
申请号 |
US19980176055 |
申请日期 |
1998.10.20 |
申请人 |
NORTEL NETWORKS LIMITED |
发明人 |
NAIR RAJESH G.;RYAN GERRY;FARZANEH FARIVAR |
分类号 |
H03M13/09;H03M13/15;(IPC1-7):H03M13/09 |
主分类号 |
H03M13/09 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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