Control system for recreating of data output clock frequency which matches data input clock frequency during data transferring

摘要

A digital data transport system where a serial stream of digital input data, received from a remote transmitter at an original clock frequency Fo, enters a FIFO repository at a variable frequency bit rate having an average frequency rate of If. A difference generator G, operating at the If frequency rate, receives a first feedback frequency clock signal Fr from a voltage controlled oscillator and a second feedback signal designating the current loading of the FIFO to provide a variable pulse stream to a driver whose output voltage controls the voltage controlled oscillator output frequency Fr so that it will match the average input frequency bit rate If (less the header bytes) in order to approximate the original clock frequency Fo.