| 摘要 |
A symmetric asynchronous interface circuit for interfacing between two asynchronously operating devices has a first and third synchronization circuits for synchronizing a READY signal outputted by a transmitting device to a clock signal on the side of a receiving device and outputting the synchronized READY signal to the receiving device, first and second delay circuits for delaying a signal corresponding to the synchronized READY signal outputted by the first/third synchronization circuit and outputting the delayed signal as an ACKNOWLEDGE signal, second and fourth synchronization circuits for synchronizing the ACKNOWLEDGE signal outputted by the first/second delay circuit to a clock signal on the side of the transmitting device, and first and second pulse generation circuits for generating a pulse signal when the synchronized ACKNOWLEDGE signal is supplied from the second/fourth synchronization circuit and outputting the pulse signal to the transmitting device as an ACKNOWLEDGE signal.
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