发明名称 |
Method of reducing word line resistance and contact resistance |
摘要 |
By introducing a carefully controlled anneal step after the deposition of tungsten silicide (onto a layer of polysilicon) but before the deposition of a layer of silicon oxide, interaction between the tungsten silicide and a subsequently deposited layer of silicon oxide is greatly reduced or eliminated. This gives good values for the resistance of gate lines formed from the composite as well as for the contact resistance between the polysilicon and the tungsten silicide.
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申请公布号 |
US6294435(B1) |
申请公布日期 |
2001.09.25 |
申请号 |
US19990414804 |
申请日期 |
1999.10.08 |
申请人 |
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
CHU HUEY-CHI;DOONG JIA-CHING;YANG CHUNG-PIN |
分类号 |
H01L21/28;(IPC1-7):H01L21/321 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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