发明名称 Vertical electrical interconnections in a stack
摘要 In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwiched self-supporting structure, wherein the layers include memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers the are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind includes the steps for adding the layers successively, one layer at a time, such that the layers form a staggered structure, and for providing one or more layers with at least one electrical contact pad for linking to one or more interlayer edge connectors.
申请公布号 AU4487701(A) 申请公布日期 2001.09.24
申请号 AU20010044877 申请日期 2001.03.15
申请人 THIN FILM ELECTRONICS ASA 发明人 PER-ERIK NORDAL;HANS GUDE GUDESEN;GEIRR I. LEISTAD;GORAN GUSTAFSSON
分类号 H01L21/3205;H01L;H01L21/00;H01L21/60;H01L23/522;H01L25/065;H01L27/00;H01L27/10 主分类号 H01L21/3205
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