CLOCK BUFFER CIRCUIT, INTERFACE HAVING THIS CLOCK BUFFER CIRCUIT, AND SYNCHRONOUS TYPE SEMICONDUCTOR STORAGE DEVICE

摘要

PROBLEM TO BE SOLVED: To suppress enlargement of chip size as far as possible and to enable reducing power consumption even if capacity is increased and function/operation is diversified. SOLUTION: This device is provided with a first delay circuit 4 receiving a clock signal CLK, a first switch circuit 8 in which opening/closing operation is performed based on the clock signal CLK and an output of the first delay circuit and the clock signal is passed and outputted in accordance with this opening/closing operation, a second delay circuit 9 receiving a clock signal which is reversed, and a second switch circuit 10 in which opening/closing operation is performed based on the reversed clock signal and an output of the second delay circuit and the reversed clock signal is passed and outputted in accordance with the opening/closing operation, the second switch circuit performs reverse opening/closing operation for opening/closing operation of the first switch circuit, and output terminals of the first and the second switch circuit are commonly connected.