发明名称 METHOD OF ADJUSTING DELAY TIME AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method of adjusting a delay time whereby the delay time of a signal can be simply and accurately adjusted and a semiconductor integrated circuit having a signal delay time adjusting circuit. SOLUTION: The purpose is attained in a layout design of a semiconductor integrated circuit by disposing a plurality of delay elements having the same driving power in series, wiring an output net so as to pass over output terminals of the delay elements, placing on signal lines a delay time adjusting circuit which connects the output terminal of one of the delay elements with the output net through a via, changing the connection of the via between the output terminal of other delay element among the plurality of delay elements and the output net according to simulation results after layout wiring, and adjusting the signal delay time, using the delay time adjusting circuit.
申请公布号 JP2001257269(A) 申请公布日期 2001.09.21
申请号 JP20000068805 申请日期 2000.03.13
申请人 KAWASAKI STEEL CORP 发明人 TAKAGAWA HIROSHI
分类号 H01L21/3205;H01L21/82;H01L21/822;H01L23/52;H01L27/04;(IPC1-7):H01L21/82;H01L21/320 主分类号 H01L21/3205
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