发明名称 METHOD OF LAYING AND WIRING SYNCHRONIZING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To enough reduce the noise of a wiring synchronizing circuit. SOLUTION: The relation of the driving powers of clock buffer cell elements of single clock buffer cells A0, A1, A2 and composite clock buffer cells B0, B1, to the capacitances of bypass capacitors respectively contained in the clock buffer cell elements of single clock buffer cells A0, A1, A2 and composite clock buffer cells B0, B1, is evaluated based on a certain reference. Consequently, capacitance lacking single clock buffer cells each lacking in capacitance of the contained bypass capacitor is detected among the single clock buffer cells A0, A1, A2, and capacitance excessive composite clock buffer cells each excessive in capacitance of the contained bypass capacitor is detected among the composite clock buffer cells B0, B1, and the positions of the capacitance lacking single clock buffer cells and the capacitance excessive composite clock buffer cells are shifted to mutually replace.</p>
申请公布号 JP2001257267(A) 申请公布日期 2001.09.21
申请号 JP20000068007 申请日期 2000.03.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRAI HIDEKI
分类号 G06F1/10;G06F17/50;H01L21/82;(IPC1-7):H01L21/82 主分类号 G06F1/10
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