| 摘要 |
PROBLEM TO BE SOLVED: To provide an effective layout method which never moves an optimum clock signal wiring layout determined by CTS (clock distributing process) in a signal wiring after CTS. SOLUTION: In the layout method, a wiring inhibit setting library 10 having information about basic cells including inhibited regions of clock signal wirings, and a library 10 having information about basic cells not including the inhibited regions of clock signal wirings, are prepared. The library 1 is used as input elements for a floor plan 4, power wirings 5, layout 6 and layout of other signal wirings 8 than clock signal wirings, and for CTS 7, the library 1 is changed to the wiring inhibit setting library 10 and this library 10 is used as input elements.
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