| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor system based on PCI bus specifications. SOLUTION: In the configuration registers 61 and 71 of bus slaves 6 and 7, a delay cycle number is stored corresponding to required memory space and I/O space. The delay cycle number is the time required after a transaction is received from a bus bridge 5 until data transfer becomes possible. A host bridge 3 reads the delay cycle number of the bus slaves 6 and 7 in a configuration cycle and stores it in the configuration register 31 as a delay cycle table. When the host bridge 3 issues the transaction, a delay cycle counter 32 starts counting the pertinent delay cycle number and the same transaction is reissued when the delay cycle number is counted up.
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