发明名称 LATCH CIRCUIT WITH ENABLE FUNCTION
摘要 PROBLEM TO BE SOLVED: To hold correct data without holding erroneous data through an enable signal borrows time. SOLUTION: A latch circuit is provided with a master latch for holding data first, a slave latch for holding data held by the master latch a half period of a clock later and a multiplexer for selecting by the enable signal whether input data is to be held by the master latch or the data held by the slave latch is to be held by the master latch. Though the enable signal borrows time and the master latch instantaneously holds the erroneous data in some clock half cycle period, the data held by the master latch can be restored to normal data immediately by making the master latch hold normal data held by the slave latch when the enable signal is made normal in the clock half cycle period. Thus, correct data can be held without holding erroneous data though the enable signal borrows time.
申请公布号 JP2001257566(A) 申请公布日期 2001.09.21
申请号 JP20000065379 申请日期 2000.03.09
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 FURUICHI WATARU
分类号 H03K3/037;(IPC1-7):H03K3/037 主分类号 H03K3/037
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