发明名称 POWER SAVING CONTROL METHOD FOR PROCESSOR, STORAGE MEDIUM AND POWER SAVING CONTROLLER FOR PROCESSOR
摘要 <p>PROBLEM TO BE SOLVED: To solve a problem that a power saving mode of a processor is not efficiently held since a hardware timer to perform timer interruption to each OS individually performs the timer interruption and simultaneously restarts the processor transited to the power saving mode in environment where the processor to be transited to the power saving mode when no task to be performed exists performs and controls plural OSs. SOLUTION: This device includes a main OS to accept the timer interruption to be outputted from the hardware timer by taking elapse of prescribed time and a sub-OS to be treated as the task to be performed by the main OS as the plural OSs to be performed and controlled by the processor, judges whether or not an executable task by taking the timer interruption exists in the main OS and when the task to be able to perform exists on the sub-OS, performs interruption to the sub-OS.</p>
申请公布号 JP2001256067(A) 申请公布日期 2001.09.21
申请号 JP20000063188 申请日期 2000.03.08
申请人 MITSUBISHI ELECTRIC CORP 发明人 KATAYAMA YOSHIAKI
分类号 G06F1/04;G06F1/32;G06F9/46;(IPC1-7):G06F9/46 主分类号 G06F1/04
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