| 摘要 |
PROBLEM TO BE SOLVED: To solve the problems that at least one defect is delay caused by accessing a requested line to a main memory in the cache memory of a computer system, a transaction activated on a bus required another bus arbitration cycle or the like and similarly a return route to the cache memory of a processor requested from the main memory requires further bus arbitration and the other delay. SOLUTION: The processor and a shared cache memory act as piers arranged between the processor and the main memory on the bus. All data arranged on the bus by the main memory as the result of a read transaction are written into the shared cache memory and the shared cache memory does not activate any transaction.
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