发明名称 MICROPROCESSOR SYSTEM
摘要 PROBLEM TO BE SOLVED: To solve the problem that a first device selection signal and the next device selection signal overlap and a mulfunction is generated when the time (phase) delay of the first device selection signal by a decoder circuit is large in the case that successive access to the next device is present after the access to the first device. SOLUTION: In this microprocessor system provided with a microprocessor 1 for controlling the plural devices 3 and 4, etc., the decoder circuit 2 for generating the device selection signals 12 and 13 for selecting an address bus from the address bus 11 is provided and a selection signal control circuit 5 for removing the delay when the delay is generated in the device selection signal 12 is provided. The edge of the device ready signal 16 of selection completion by the device selection signal 12 is captured (differentiation operation), the device selection signal 12 is forcibly interrupted after counting specified time and overlap with the next device selection signal 13 is eliminated.
申请公布号 JP2001256103(A) 申请公布日期 2001.09.21
申请号 JP20000065551 申请日期 2000.03.09
申请人 YASKAWA ELECTRIC CORP 发明人 MATONO MASAO
分类号 G06F13/14;G06F12/00;G06F13/362;(IPC1-7):G06F12/00 主分类号 G06F13/14
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