| 摘要 |
PROBLEM TO BE SOLVED: To solve the problems that an integrated cache memory is provided with many address connections, logic for comparing the addresses of respective address buses is required in order to detect address contention, 'NC2' pieces, that is N(N-1)/2 pieces, of comparator circuits are required in the case that there are N pieces of the address buses, the number of the required comparator circuits increases when the number of the address buses increases and thus it is desired to reduce the comparator circuits. SOLUTION: This device is provided with a multiplexer and a logic circuit. The multiplexer is connected to the plural address buses and provided with a control input part and a memory connection part and the logic circuit generates output signals connected to the control input part. One of the plural address buses is selectively connected to a memory by the output signals.
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