发明名称 FIFO MANAGEMENT METHOD AND PIPELINE PROCESSOR SYSTEM
摘要 PROBLEM TO BE SOLVED: To improve the fault of a conventional pipeline system. SOLUTION: This method and a device 20 for improving the performance of a pipeline system for which a FIFO 24 is connected in a pipeline between an upstream processing module 22 and a downstream processing module 26 in the pipeline system are disclosed. Each module accesses a common external memory 32 and it is regularly observed in many ASIC. The method is started by detection when the vacancy of the FIFO 24 is practically gone and a command is transferred from the upstream module 22 to the external memory 32. The command respectively from the FIFO 24 and the external memory 32 received by the downstream module 26 is analyzed and the existence location of the following command of the command is decided.
申请公布号 JP2001256200(A) 申请公布日期 2001.09.21
申请号 JP20010036104 申请日期 2001.02.13
申请人 CANON INC 发明人 LIE KOK TJOAN
分类号 G06F9/38;G06F5/06;G06F13/14;G06F15/00;G06F15/16;G06F15/80;(IPC1-7):G06F15/16 主分类号 G06F9/38
代理机构 代理人
主权项
地址