A memory address generator (12) generates a memory address. A multiplier (15) reads out the value of a replacing pattern of a row corresponding to a row number outputted from a memory (14) where the row-replacing pattern of a matrix is stored through a row counter (11) and multiplies the value of the replacing pattern of the row thus read out by the number of columns of the matrix to calculate an address offset value. An adder (16) reads out the value of a replacing pattern of a column corresponding to the memory address generated by the address generator from a memory (13) where the replacing pattern of a column of the matrix is stored and adds the value of the replacing pattern of the column thus read out to the address offset value thus generating an interleave address.
申请公布号
WO0169794(A1)
申请公布日期
2001.09.20
申请号
WO2001JP02146
申请日期
2001.03.19
申请人
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;IKEDA, TETSUYA;SUZUKI, HIDETOSHI;YAMANAKA, RYUTARO;KURIYAMA, HAJIME