BIP-N processing apparatus and BIP-N processing method therefor

摘要

In a Bit Interleaved Parity (BIP)-N calculating apparatus (N is an integer) according to the present invention, serial/parallel conversion circuit 1 performs a byte-interleaved separation on input STS-3c concatenated signals. The separated signals are supplied to the serial/parallel conversion circuits 2 to 4 where these signals are subjected to a bit-interleaved separation to attain N-bit signals. Each serial/parallel conversion circuit respectively provides the N-bit signal to BIP-N calculation circuit 5 to 7. Outputs from the BIP-N calculation circuit 5 to 7 are held in flip-flops 8 to 10 and then supplied to exclusive-OR gates 11 to 13. The exclusive-OR gates 11to 13 and concatenation control circuits 14 to 16 are connected in a concatenation manner, so that a calculation is performed in a concatenation manner on the results of the BIP-N calculation circuits 5 to 7. The EX-OR gate 11 outputs a signal as the BIP-N calculation result.