| 摘要 |
<p>A Viterbi decoder in which error correction characteristics can be improved while increase of system scale is suppressed. The device is provided with a bit range conversion part (11) for converting the bit range of branch metric values calculated by a branch metric calculation part (1) to match the bit range with the number of bits calculated used for an ACS part (2), between the calculation part (1) and the ACS part (2). Until a frame is completed, the received data is read to calculate the branch metric, to optimize the branch metric, to change a path metric, and to store the path metric. When the frame is completed, the result of decoding is outputted by back-tracing.</p> |
