发明名称 HARDWARE ARCHITECTURE AND METHOD FOR DISTRIBUTED MACHINE CONTROL
摘要 A hardware architecture links control modules to a host computer in a high-speed serial bus network to achieve efficient distributed machine control. Each control module includes a communications unit and a function unit that are coupled to each other as a part of the control module. All communications units are similarly constructed with each having a unique identification set by a component thereof and provide communications between control modules and the host computer. The function unit of each control module is distinctly configured for executing functions specific to the particular control module to which it is attached. The high-speed serial bus provides deterministic synchronization of data transfers between control modules and the host computer using either an isochronous mode and protocol or an asynchronous mode with a fixed real-time clock issuing data requests at fixed time intervals. Data transfers do not require host computer involvement and can occur directly between control modules. Each control module maintains data blocks containing the desired control status from the host computer and the current state of all variables related to the particular control module. These data blocks are available to the host computer and each control module at fixed time intervals without the need for data requests. This permits near real-time intervention or change of state within the controlled machine processes.
申请公布号 WO0169333(A2) 申请公布日期 2001.09.20
申请号 WO2001US07236 申请日期 2001.03.06
申请人 META CONTROLS, INC. 发明人 HUDSON, EDISON, T.;MCCORMICK, JAMES;GENISE, RONALD, G.;DAHL, JEROME
分类号 G05B19/042;(IPC1-7):G05B19/042 主分类号 G05B19/042
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