| 摘要 |
The invention concerns a new bus protocol for the serial transfer of data between two electronic components (SLAVE, MASTER) via a 3 line bus connection. According to a known bus protocol each transfer of a data bit is accompanied by handshake signals which makes the data transfer slow. The bus protocol according to the invention does without handshake signals for each bit. Each data word is transferred synchronously from transmitter to receiver. One bus line (CLK) is therefore dedicated to a clock signal. The two other bus lines (SD, MD) are used for transmitting the data signals and control signals. By assigning the two remaining bus lines (SD, MD) differently to data signals and control signals for the both transfer directions, bus conflicts can be easily solved. The invention also concerns an advantageous bus station.
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