| 摘要 |
A cache memory system comprises a cache 4, a prefetch store 5, and a memory controller 3. The controller 3 receives requests from a processor 1 for access to lines of data stored in a memory 2 and maintains priority data indicative of the relative priority of lines of data stored in the cache 4. The controller 3 responds to receipt of a processor request for access to data in a line N such that: for a cache hit, the controller supplies the data from the cache 4 to the processor 1; for a cache miss when line N is not stored in the prefetch store 5, the controller 3 retrieves line N from the memory, and controls storage of the line in the cache 4 and supply of the data to the processor 1, the priority data for line N being set to a high relative priority; for a cache miss when line N is stored in the prefetch store 5, the controller 3 transfers line N from the prefetch store 5 to the cache 4 and supplies the data to the processor 1, the priority data for line N being set to a low relative priority; and for both a cache hit and a cache miss, the controller 3 prefetches the sequentially next line N+1 from the memory 2 to the prefetch store 5. Prefetching is preferably only performed for a defined subset of the lines in the memory.
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