发明名称 |
Delay control circuit synchronous with clock signal |
摘要 |
A delay line for forward pulse has a plurality of delay units for forward pulse. A delay line for backward pulse has a plurality of delay units for backward pulse. In the delay line for backward pulse, a pulse signal is propagated in an opposite direction to a direction of the propagation in the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for forward pulse is set to be parallel to a direction of the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for backward pulse is set to be parallel to a direction of the delay line for backward pulse. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for forward pulse are set to be opposite to one another. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for backward pulse are set to be opposite to one another.
|
申请公布号 |
US6292411(B1) |
申请公布日期 |
2001.09.18 |
申请号 |
US20000537424 |
申请日期 |
2000.03.27 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
KAMOSHIDA MASAHIRO;AKITA HIRONOBU |
分类号 |
G11C11/407;G06F1/10;G11C7/22;G11C8/00;G11C11/401;H01L21/82;H01L21/822;H01L27/04;H03K5/135;H04L7/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/407 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|