| 摘要 |
The invention provides methods and apparatus for implementing a satisfiability algorithm on reconfigurable hardware. An illustrative embodiment is in the form of a parallel-backtrace satisfier which includes clause logic, literal logic and variable logic for implementing logic functions associated with clauses, literals and variables, respectively, of a circuit to be analyzed. The satisfier also includes a controller, e.g., a synchronization unit, for directing the operation of the clause logic, literal logic and variable logic so as to provide parallel backtracing of objectives along a plurality of circuit paths from a primary output of the circuit toward its primary inputs. Enhanced parallelism is implemented in the illustrative embodiment not only by providing the parallel backtracing of the multiple objectives, but also by, e.g., providing concurrent assignments of multiple primary inputs. The clause logic, literal logic and variable logic may each be implemented using easily-scalable iterative logic array (ILA) structures including multiple cells, with each cell representative of a logic function associated with the processing of a corresponding clause, literal or variable of the circuit to be analyzed.
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