发明名称 Methods for determining on-chip interconnect process parameters
摘要 A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.
申请公布号 US6291254(B1) 申请公布日期 2001.09.18
申请号 US19990244616 申请日期 1999.02.04
申请人 SEQUENCE DESIGN, INC. 发明人 CHOU SHIH-TSUN ALEXANDER;CHANG KEH-JENG;MATHEWS ROBERT G.
分类号 H01L23/544;(IPC1-7):G01L21/66 主分类号 H01L23/544
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