| 摘要 |
A synchronous semiconductor memory device such as SDRAM easy in timing adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.
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