| 摘要 |
A memory system with an operating voltage of Vcc has a memory cell with first and second inverters connected input to output to make a latch defining a Q node and a QB node, and powered by a single voltage controlled Vmm line. There is a passgate transistor connected source to drain from a BIT line to the first inverter, the passgate having a strength low enough that, with Vmm substantially equal to Vcc and the gate of the passgate energized at Vcc by a WORD signal, no signal on the BIT line can flip the latch. Circuitry is provided for reducing the voltage of Vmm during a write cycle, so a signal on the BIT line may flip the latch. In preferred embodiments the memory system is applied to Programmable Logic Arrays.
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