| 摘要 |
A circuit for signalling if any like ordered bits Ak and Bk in first and second binary words differ comprises a comparator for each pair of like ordered bits and a common terminal. Each comparator includes first and second FETs arranged so: (a) the first and second levels of Ak are coupled to the common terminal via the first FET in response to Bk having the first value, (b) the first and second levels of Bk are coupled to the common terminal via the second FET in response to Ak having the first value, (c) the first FET decouples Ak from the common terminal and tends to cause the common terminal to be at the second level in response to Bk having the second value, (d) the second FET decouples Bk from the common terminal and tends to cause the common terminal to be at the second level in response to Ak having the second value, and (e) the common terminal is at the second level only in response to Ak <CUSTOM-CHARACTER FILE="US06292093-20010918-P00900.TIF" ID="CUSTOM-CHARACTER-00001"> Bk. A FET connected as a diode and coupled between the common terminal and each of the FETs maintains the common terminal at the second value in response to Ai <CUSTOM-CHARACTER FILE="US06292093-20010918-P00900.TIF" ID="CUSTOM-CHARACTER-00002"> Bi, where i is any value of k.
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