发明名称 |
Tcl pli, a framework for reusable, run time configurable test benches |
摘要 |
A scripting approach to managing the test bench complexity issue is provided. Partitioning the functionality of a test bench between Verilog and a scripting language allows for a significant reduction in compile times during ASIC verification. If done correctly, partitioning also offers great potential for re-use of test bench components. The Tcl language was chosen as a basis for implementing a library of PLI routines that allow fully customizable interpreters to be instantiated in Verilog test benches. This library allows multiple Tcl interpreters to be instantiated in a Verilog simulation. The Tcl interpreters can interact with the simulation and cause tasks to be executed in the Verilog simulation. It has been found the TCL_PLI library is extremely valuable in speeding up verification efforts on multi-million gate ASICs. |
申请公布号 |
AU3702701(A) |
申请公布日期 |
2001.09.17 |
申请号 |
AU20010037027 |
申请日期 |
2001.02.15 |
申请人 |
ELECTRONICS FOR IMAGING, INC. |
发明人 |
STEPHAN VOGES;MARK ANDREWS |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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