发明名称 FIXED DELAY LOOP
摘要 PROBLEM TO BE SOLVED: To provide a fixed delay loop which has a small signal jitter and a stable time delay control function and can realize bi-directional time delay with a small area against a low frequency. SOLUTION: The fixed delay loop is provided with an input means 400 to which a clock signal clk and an inverted clock signal clkb are inputted, which compares the inputted signals with each other and generates an inner clock, a control means 410 to which the inner clock is inputted and which generates a control signal, a bi-directional oscillator 421 controlling the increase/decrease of time delay while ring oscillation is performed in a first direction and a second direction in response to the control signal outputted from the control means 410, a counter comparator 424 counting the number of rotation times by the input of a signal outputted from the bi-directional oscillator 421 and comparing the number of counting with each other times and an output means 425 combining the outputs of the bi-directional oscillation means 421 and the counter comparator 424 and outputting a final inner clock signal.
申请公布号 JP2001251172(A) 申请公布日期 2001.09.14
申请号 JP20000393046 申请日期 2000.12.25
申请人 HYNIX SEMICONDUCTOR INC 发明人 LEE SEONG-HOON
分类号 G11C11/413;G06F1/10;G11C7/22;G11C11/407;G11C11/4076;H03K5/131;H03K5/135;H03K5/14;H03L7/00 主分类号 G11C11/413
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