发明名称 INPUT PACKET PROCESSING SYSTEM FOR PACKET SWITCH
摘要 <p>PROBLEM TO BE SOLVED: To prevent MPLS packets executed through a plurality of number of times of hop processing in an LSR from affecting a processing start time of packet reaching later. SOLUTION: The packet switch is provided with a pipeline P1 that discriminates an operation to be executed among swap, push and pop operations on the basis of contents of a shim header of an MPLS packet and information set in advance, and that acquires information required for the execution and acquires output path information in a way of a flow process. A header controller 7 sequentially inputs a head shim header of each packet received from a plurality of channels 2 to the pipeline P1 and applies an actual operation to the head shim header of each packet on the basis of the obtained information. When a shim header newly comes to the head as a result of a pop operation, input processing of the shim header is again repeated to the pipeline P1. That is, the pop processing of the MPLS packet is not conducted by batch system but conducted while looping the pipeline.</p>
申请公布号 JP2001251351(A) 申请公布日期 2001.09.14
申请号 JP20000061806 申请日期 2000.03.02
申请人 NEC CORP 发明人 SHIODA YOSHIAKI
分类号 H04L29/02;H04L12/66;H04L12/70;(IPC1-7):H04L12/56 主分类号 H04L29/02
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