INTERLACED MULTI-LEVEL MEMORY

摘要

A memory device (700) having a plurality of multi-bit cells (702) that are programmed with interlaced data provide superior read access time. The multi-bit cells (702) are read by reading the first bit of each of the plurality of cells sequentially using a first reference voltage than reading the second bit of a first subset of the plurality of cells (702) sequentially using a second reference voltage than reading the second bit of a second subset of the plurality of cells (702) sequentially using a third reference voltage. The second reference voltage being higher and the third reference voltage being lower than the first reference voltage.