A semiconductor memory the cycle time of which is shortened by accelerating the address access. A first address decoder (2) and a first refresh address decoder (5) decode an external address (Xn) fed from outside of the semiconductor memory and a refresh address (RXn) used for refresh in the semiconductor memory, respectively. A multiplexer (8) selects either a decode signal (XnDm) on the external address side or a decode signal (XnRm) on the refresh address side according to an external address transmission signal (EXTR) and a refresh address transmission signal (RFTR) so that a refresh and a Read/Write may be continuously performed in one memory cycle, and outputs the selected one as a decode signal (XnMm). A word driver (10) decodes the decode signals (XnMm, XpMq) selected by the multiplexer (8) and so forth so as to activate a word line (WLmq).
申请公布号
WO0167461(A1)
申请公布日期
2001.09.13
申请号
WO2001JP01768
申请日期
2001.03.07
申请人
NEC CORPORATION;TAKAHASHI, HIROYUKI;INABA, HIDEO;SONODA, MASATOSHI;KATO, YOSHIYUKI;NAKAGAWA, ATSUSHI